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Pongo una serie de ejemplos, no necesariamente relacionados entre sí. Necesito una formulación genérica para "it is noted that", que tenga un estilo apropiado.

Crossbar interconnect technology has been developed in recent years with a primary focus in applications in information storage and retrieval. A crossbar array basically comprises a first set of conductive parallel wires and a second set of conductive parallel wires formed so as to intersect the first set of conductive wires. The intersections between the two sets of wires are separated by a thin film material or molecular component. A property of the material, such as the material's resistance, may be altered by controlling the voltages applied between individual wires from the first and second set of wires. Alteration of the materials resistance at an intersection may be performed so as to achieve a high resistance or low resistance state and thus store digital data. It is noted that crossbar arrays are occasionally referred to as cross point or crosswire arrays.

FIG. 2a-2c illustrates the internal workings of a crossbar array used in accordance with the present invention. As illustrated in FIG. 2a, a 3×8 crossbar array includes three parallel input wires, 8 parallel output wires, 8 parallel programming wires, and 3 parallel ground connection wires. The output wires are formed so as to intersect the input wires at 24 (8×3) crosspoints. Between the input wires and output wires a material 205 with programmable resistance is formed and the state of resistance of a particular crosspoint determines if high or low conduction will occur between the associated input wire and output wire at this point. Similarly, the programming wires and ground connection wires are formed so as to intersect and are used to set the initial resistance states of the 24 crosspoints. It is noted that the circuit formed via the input wires and the output wires is preferably operated at separate times from the circuit formed by the programming and ground connection wires. In addition these circuits are preferably electrically isolated by providing different grounds and driving sources so as to minimize any possible electrical interference.

FIGS. 9a and 9b illustrates an interface circuit configuration used to connect an 8×15 crossbar array such as in FIG. 8 with a 15×18 crossbar array. As in the post-processing circuit of FIG. 6, transistors 901 are provided to facilitate clearing of the 8×15 crossbar array and op-amps 902 facilitate the summing action of the voltage states for each row. However, in this case four bit A/D converters 903 are used since 9 possible analog values are possible at the input. Given the nature of the multiplication process in which data sums on the upper and lower rows are relatively low, whereas data sums toward the middle row are high, alternative circuit construction may use a 1-bit A/D converter for the first and fifteenth rows, a 2-bit A/D converter for the second, third, thirteenth, and fourteenth rows, a 3-bit A/D converter for the fourth-seventh and ninth-twelfth rows and a 4-bit A/D converter for the eighth row, which may beneficially result from less circuit complexity. However, using a common A/D converter resolution allows the possibility of applications in summing and integration processes, in which the data quantity is not weighted toward the middle rows. Logic AND gates 904 are used to control the load timing of each of the outputs of the A/D circuits into a column of the 15×18 crossbar array. Signal LOADpA provides loading of the first column of the 15×18 crossbar array with data prog1A-prog4A, signal LOADpB provides loading of the second column of the 15×18 crossbar array with data prog2B-prog5B, signal LOADpC provides loading of the third column of the 15×18 crossbar array with data prog3C-prog6C, etc., up to signal LOADpO which loads the last column with data prog15O-prog18O. Logic OR gates 905 in FIG. 9b determine the relative position of the four bit data within a particular column and voltage transformation circuitry 906 transforms the voltage values from a logic HIGH magnitude to a sufficient drive voltage so as to alter the programmable material resistance within the selected crosspoints of the crossbar array. Signals prog1-prog18 thus set the crosspoint resistance state for a selected column of the 15×18 crossbar array. It is noted that instead of using the AND and OR gate arrays the outputs from the A/D converters 903 may be temporarily stored in respective addresses of a data register and recalled when programming the columns of the 15×18 crossbar array.

Division may be performed by a crossbar processor by diagonally programming a binary numerical value in the columns of the crossbar array, as was done in the multiplication processes, and altering the input to the crossbar array while comparing the product obtained with the intended number to be divided. FIG. 16 illustrates a 4×7 crossbar array used in a division procedure and FIG. 17 illustrates a flowchart of the division procedure. In this example the programmed data is 1101 representing a divisor of 13 and the number to be divided (i.e. dividend) is 1011011 representing numeral 91. The input data is set to initially set to 0000, and i represents the bit number from the most significant bit (i=1) to the least significant bit (i=4). In steps S1701 and S1702 the MSB is set to 1 and the product is calculated using the crossbar processor (S1703). The product 1101×1000 produces the result 1101000. Comparison of this value to the dividend 1011011 (S1704) may be performed by comparing the bit values in the order from the most significant value to the least significant value with an array of comparator circuits or by a general purpose microprocessor. In the case that the product is detected to be larger than the dividend, input(i) is set back to 0 (S1705) and the bit position being examined is incremented (S1706). In the case that the product is detected to be smaller than the dividend, input(i) remains at 1. In step S1707 if the bit position being examined is greater than the maximum bit number (in this case 4) the process is ended (S1708). For the current example the process goes through four iterations testing the values of 1000, 0100, 0110, and finally 0111 for a total of four iterations. In this case, the process stops based on step S1704 in which it is found that the calculated product equals the dividend. The quotient is then equal to the final iteration of the input. In a case where there is a remainder this may be calculated based on the difference between the dividend and the calculated product. It is noted that the algorithm of FIG. 17 may also be applicable to conventional arithmetic processors for increased speed of division processing.

It is noted that when dealing with a large number of nodes in the above examples, the techniques of genetic algorithms maybe used to help find the optimum sum. For example, taking the node arrangement of FIG. 19, the columns of a crossbar array may be programmed with the numerical values associated with d(A,B), d(A,C), d(A,D), d(A,E), d(B,C), etc. in such an order that the first four columns contain the inter-node factors leading out from node A, the second four columns contain the inter-node factors leading from node B, the third four columns contain the inter-node factors leading from node C, etc. Programming the columns in such a fashion, the numerical sum associated with the path shown in FIG. 19 may be calculated by inputting 1000 1000 0100 0010 0001 into the crossbar processor. Inputting 0001 0001 0100 1000 0100 results in another possible path equivalent to d2(A,F) noted above. While not all possible binary inputs result in valid paths from node A to node F, certain rules may be formulated to determine or check whether a particular binary pattern is representative of a legitimate path. The set of all valid inputs may be used to form a population of possible solutions to be checked by the crossbar arithmetic processor. While the case of only 4 intermediate nodes contains only 24 possible solutions to be checked, an increase in the node number quickly raises the number of possible solutions. In this case a random subset of the possible solution population may be selected. Processing each of these inputs by a crossbar arithmetic processor and comparison of the results may be used as an evaluation step. Recombination may be performed by appropriately mixing bit segments of the inputs that produced the most highly evaluated outputs and creating a next population to be evaluated. If poor evaluation is found for the current population mutation may optionally be performed by adding other permissible binary inputs to the population. The repeated cycle of evaluation, recombination, and mutation may be performed until a sufficiently optimized path is found.